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Description: 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
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Size: 473099 |
Author: Jack |
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Description: spi接口的vhdl实现，所用器件和ip为xilinx的
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Size: 3112742 |
Author: 杨子树 |
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Description: SPI经典ip核
可以直接用于工程的开发和利用
Platform: |
Size: 49698 |
Author: 毋杰 |
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Description: 讲述Windows网络程序设计的入门教程，展示了各种Windows I/O的方法，详细说明了高性能可伸缩性服务器的开发过程，并给出详细的实现代码。将编程方法、网络协议和应用实例有机组合起来，详细介绍了Internet广播和IP多播、原始套接字、SPI、LAN和WAN上的扫描和侦测技术、网络数据的窃取和保护、ARP欺骗、IP欺骗等。详细演示了协议驱动的开发过程，介绍了NDIS编程接口。在编程实践中学习P2P程序设计、讨论了穿透防火墙、NAT等直接建立UDP和TCP连接的各种方案。包含了Windows个人防火墙的完整实例代码，防火墙采用应用层（SPI）核心层（IMD驱动）双重过滤机制，能够有效地抵挡网络入侵和攻击。提供了大量的完整的实例，许多例子稍做修改即可应用到实际项目中。-on Windows network programming tutorial for beginners, Windows display a variety of I/O methods, a detailed description of high-performance, scalable server development process, and gives detailed codes. Will be programming, network protocol and application examples of organic composition, Details on the Internet radio and IP Multicasting, the original socket, SPI, LAN and WAN on the scanning and detection technology, network and data theft protection, to deceive the ARP, IP deception. Details of the agreement demo-driven development process, NDIS Programming Interface. Programming in practice learning P2P program design, discussed the penetration of firewalls, NAT establish direct UDP and TCP connections to the various programs. Windows includes a complete personal firewall code example
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Size: 2154496 |
Author: 王勇 |
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Description: 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
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Size: 473088 |
Author: Jack |
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Description: 如题所示.可复用SPI模块IP核的设计与验证-Such as the title indicated. SPI module reusable IP core design and verification
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Size: 81920 |
Author: allen |
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Description: 15个IP核，很难找到的东西，找了很久得东西-15 IP core, it is difficult to find things for a long time to find a thing
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Size: 2644992 |
Author: peter |
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Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
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Size: 1024 |
Author: linsky |
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Description: spi接口的vhdl实现，所用器件和ip为xilinx的-spi interface VHDL realize, by ip for Xilinx devices and the
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Size: 3112960 |
Author: 杨子树 |
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Description: SPI经典ip核
可以直接用于工程的开发和利用-err
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Size: 49152 |
Author: 毋杰 |
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Description: spi controller
SPI IP core
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Size: 81920 |
Author: denny |
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Description: SPI IP core supporting SD/MMC
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Size: 2269184 |
Author: zhanglh |
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Description: this code shows how to use the ENC28J60 mini library :
* the board will reply to ARP & ICMP echo requests
* the board will reply to UDP requests on any port :
* returns the request in upper char with a header made of remote host IP & port number
*
* target devices :
* any PIC with integrated SPI and more than 4 Kb ROM memory
* 32 to 40 MHz clock is recommended to get from 8 to 10 Mhz SPI clock,
* otherwise PIC should be clocked by ENC clock output due to ENC silicon bug in SPI hardware
* if you try lower PIC clock speed, don t be surprised if the board hang or miss some requests !
* tested with PIC16F877A@10Mhz on EasyPIC3 board-this code shows how to use the ENC28J60 mini library :
* the board will reply to ARP & ICMP echo requests
* the board will reply to UDP requests on any port :
* returns the request in upper char with a header made of remote host IP & port number
*
* target devices :
* any PIC with integrated SPI and more than 4 Kb ROM memory
* 32 to 40 MHz clock is recommended to get from 8 to 10 Mhz SPI clock,
* otherwise PIC should be clocked by ENC clock output due to ENC silicon bug in SPI hardware
* if you try lower PIC clock speed, don t be surprised if the board hang or miss some requests !
* tested with PIC16F877A@10Mhz on EasyPIC3 board
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Size: 2048 |
Author: duonghai |
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Description: spi经典IP核, spi经典IP核.-spi classical IP core, spi classical IP core, spi classical IP core.
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Size: 49152 |
Author: zhangkaibo |
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Description: 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
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Size: 49152 |
Author: wuyou |
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Description: PIC单片机网络编程的源代码，使用了EN28J60以太网控制器，非常适合远程控制场合，ENC28J60是一款专门为单片机应用而设计的以太网控制芯片，一共28个引脚，通过SPI总线与单片机芯片连接，占用口线少，速度也比较快，对于软件开发而言，MicroChip提供了免费的TCP/IP协议栈，大大方便了软件工程师的开发工作。-PIC microcontroller network programming source code, use the EN28J60 Ethernet controller, ideal for remote control of occasions, ENC28J60 is an application designed specifically for single chip Ethernet controller chip, a total of 28 pins, through the SPI bus and single chip connection, taking up less port line speed is also faster for software development purposes, MicroChip provides a free TCP/IP protocol stack, which greatly facilitate the development of software engineers.
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Size: 1726464 |
Author: zhouyao |
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Description: SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
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Size: 1487872 |
Author: thegreeneyes |
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Description: SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
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Size: 628736 |
Author: 任林枫 |
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Description: 比较经典实用的ip核，对初学者有很大的帮助，语言比较简单。-Classic and practical IP core, a great help for beginners, the language is relatively simple.
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Size: 50176 |
Author: 张三 |
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Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。
SPI相关缩写
SS: Slave Select，选中从设备，片选。
CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性
CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位
SCK = SCLK = SCL = SPI的时钟（Serial Clock）
Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。
对于一个时钟周期内，有两个edge，分别称为：
Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候；
Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices.
SPI related abbreviations
SS: Slave Select, selected from the device, chip select.
CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity
CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase
SCK = SCLK = SCL = SPI clock (Serial, Clock)
Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge).
For a clock cycle, there are two edge, respectively:
Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1;
Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;)
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Size: 6144 |
Author: helimpopo
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